A CMOS field-effect transistor may include a high-k gate dielectric and metal gate electrodes. The metal gate electrodes may be formed from different metals using a replacement gate process. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed to create a trench between the spacers. The trench is lined with a high-k gate dielectric layer and then filled with a first metal. After a second polysilicon layer is removed, the resulting trench is lined with a high-k gate dielectric layer and filled with a second metal that differs from the first metal. When such a process forms the high-k gate dielectric layer on a chemically treated substrate, the resulting transistor may be unreliable.
Rather than apply a replacement gate process to form a metal gate electrode on a high-k gate dielectric layer, a subtractive approach may be used. In such a process, a metal gate electrode is formed on a high-k gate dielectric layer by depositing a metal layer on the dielectric layer, masking the metal layer, and then removing the uncovered part of the metal layer and the underlying portion of the dielectric layer. Although a transistor formed using such a process may be reliable, it may not provide optimum performance.
Accordingly, there is a need for an improved process for making a semiconductor device that includes a high-k gate dielectric and a metal gate electrode. There is a need for such a process that may generate a high performance device, which is also reliable. The method of the present invention provides such a process.
Features shown in these figures are not intended to be drawn to scale.